In the design of a System-on-Chip (SoC), the digital part can be treated by partitioning into various sub-systems. Each sub-system satisfies respective given constraints in regards to the interface boundary so that in the integration stage it is possible to obtain the “timing closure” in a straightforward way. For example, an important constraint is that the interface signals can come directly from flip-flops without assuming output delays in this layer.
Satisfying this constraint is generally possible, but in the case of the control paths, important aspects can arise. These aspects are linked to the possible presence, between two parts of the system, of logic alone so as to reduce latency. This can create integration problems for high-frequency applications and when the Intellectual Property (IP) modules communicate with the bus using a protocol with request-grant validation. In this way, the IP modules prepare new data using the slow grant signal coming from the bus.
Techniques of a first-in first-out (FIFO) type using a fixed output position may be used. In this case, the function of timing closure is simpler in that the grant signal coming from the bus is loaded only in this module.
However, there are disadvantages associated with this approach. In particular, the presence of a specific FIFO scheme renders loading of the data in the read stage more complex. Furthermore, the function of timing closure is satisfactory on the data path but the shift operation for shifting the data in the fixed location imposes a certain load on the grant signal, which is assumed to arrive with a delay from the bus.
Other approaches use FIFO schemes on two locations to overload the ACK signal only in the selection of one of the two data locations through updating of a read pointer. However, these approaches are important in regards to management of the pointers. There is a risk of injecting “bugs” in the overflow/underflow of the pointers themselves. A modular approach does indeed enable saving of time, but cannot be implemented within an IP module for insuring the minimum latency possible in a scheme that is aimed exclusively at optimizing the timing. Representative of the relevant art are U.S. Pat. Nos. 6,834,378 and 6,956,424.